by barkkathulla 2012-09-21 09:52:30

The same time, a transition is occurring in SoC implementation. Designs in markets from communications to consumer and automotive are moving from ASICs to FPGAs due to increasing mask and silicon costs. As ASIC development costs increase, the break-even volume required to justify the expense is also increasing, pushing a larger number of designs into programmable devices. The same market and process dynamics that are causing ASIC costs to increase are also reducing the cost per gate of FPGAs. This boosts the level of integration, leading to larger devices that can support complex system-level applications. Just a few years ago, such applications could only be implemented in ASICs. When coupled with the fast time-to-market that FPGAs offer, this implementation shift will continue, presenting programmable logic vendors with a huge market opportunity. Even with these trends, there has been, until now, a challenge: a majority of portable designers have implemented their devices using a microcontroller in conjunction with a programmable logic device. They have used the microcontroller to implement the necessary processing, and have programmed the FPGA with additional application-specific features and functions not supported by the microcontroller. That issue is rapidly fading. Smaller cores, better IP and development environments, and the double-time march of technology has created a situation in which processor and controller cores can now be part and parcel of FPGAs. The combination of the ARM Cortex-M1 processor with low-power Actel IGLOO® and Fusion® mixed-signal FPGAs provides a single-chip solution that reduces cost, power, board space, and design complexity. It also broadens a designer's application reach and time-to-market. Figure 1: Percentage of ASIC Designs Using Microprocessors 4 Developing Embedded Applications with ARM Cortex-M1 Processors in Actel IGLOO and Fusion FPGAs It is commonplace now for FPGA vendors to include processor or MCU cores for their customers, but there are two distinct camps playing this game. In the first camp, the IP provided for the FPGA is proprietary. These cores are tightly controlled, optimized, and vetted by the FPGA vendor. The challenge associated with proprietary architectures is making them efficient in targeted applications and putting tools in place to support them. Experienced engineers know that there is a learning curve when using anything new; it takes time to climb the learning curve and gain the experience to deal with the product's unique characteristics.

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